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TS4872
RAIL TO RAIL INPUT/OUTPUT 1W AUDIO POWER AMPLIFIER WITH STANDBY MODE
NOT FOR NEW DESIGN
OPERATING FROM VCC = 2.2V to 5.5V RAIL TO RAIL INPUT/OUTPUT 1W OUTPUT POWER @ Vcc=5V, THD=1%,
f=1kHz, with 8 Load MODE (10nA)
PIN CONNECTIONS (Top View)
ULTRA LOW CONSUMPTION IN STANDBY 75dB PSRR @ 217Hz @ 5 & 2.6V ULTRA LOW POP & CLICK ULTRA LOW DISTORTION (0.05%) UNITY GAIN STABLE 8 X170m BUMPS FLIP CHIP PACKAGE
DESCRIPTION
8
Vout1
7
Vin
+
IG
6 5
Vcc STDBY Vout2 GND BYPASS
S
Vin
This Audio Amplifier is exhibiting 0.1% distortion level (THD) from a 5V supply for a Pout = 250mW RMS. An external standby mode control reduces the supply current to less than 10nA. An internal shutdown protection is provided. The TS4872 has been designed for high quality audio applications such as mobile phones and to minimize the number of external components.
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The unity-gain stable amplifier can be configured by external gain setting resistors.
Portable Audio Devices
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APPLICATIONS
Mobile Phones (Cellular / Cordless) PDAs Laptop/Notebook computers
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The TS4872 is an Audio Power Amplifier capable of delivering 1W of continuous RMS Ouput Power into 8 load @ 5V.
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TYPICAL APPLICATION SCHEMATIC
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Audio Input Cin Rin 1 7 VinVin+ +
Cfeed Rfeed Vcc 6 Cs
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Vcc
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4
Vout1 8 RL 8 Ohms Vout2 4 TS4872
TS4872IJT - FLIP CHIP
Vcc 3 Bypass Standby Bias
Av=-1 +
ORDER CODE
Part Number TS4872IJT Temperature Range -40, +85C Package Marking J YW4872
Rstb 5
Cb
J = Flip Chip Package - only available in Tape & Reel (JT)
April 2005
GND
2
1/29
TS4872
ABSOLUTE MAXIMUM RATINGS
Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Latch-up Supply voltage Input Voltage
2) 1)
Parameter
Value 6 -40 to + 85 150
Unit V
Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip Chip Thermal Resistance Junction to Ambient Power Dissipation Human Body Model Machine Model Latch-up Immunity Lead Temperature (soldering, 10sec)
3)
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GND to VCC
V C C C C/W kV V C
OPERATING CONDITIONS
Symbol VCC VICM Supply Voltage Common Mode Input Voltage Range VCC from 2.6V to 5V VCC < 2.6V Standby Voltage Input : Device ON Device OFF Load Resistor Parameter
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1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / G ND - 0.3V 3. Device is protected in case of over temperature by a thermal shutdown active @ 150C
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Internally Limited 2 200 Class A 250
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200 2.2 to 5.5 GND to VCC VCC / 2
-65 to +150
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Value
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Unit V
VSTB RL Rthja
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Flip Chip Thermal Resistance Junction to Ambient
1. With Heat Sink Surface = 125mm 2
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2/29
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GND VSTB 0.5V VCC - 0.5V VSTB VCC
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C/W
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TS4872
ELECTRICAL CHARACTERISTICS VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N PSRR Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, f = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Parameter Min. Typ. 6 10 5 1 0.1 75 70 Max. Unit mA nA mV W % dB
IG D E S W
20 2
Power Supply Rejection Ratio 2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8
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GM GBP
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1000 20 Max. 8 1000 20
8
R
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz
ICC ISTANDBY Voo Po
Supply Current No input signal, no load
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Symbol
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VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified) 3)
Parameter
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Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8
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THD + N PSRR
Output Power THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Power Supply Rejection Ratio 2) f = 217Hz, RL = 8, RFeed = 22Ks, Vripple = 100mV rms
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Degrees dB
MHz
Typ. 5.5 10 5 450 0.1 68 70 20 2
Unit mA nA mV mW % dB Degrees dB MHz
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Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8
GM GBP
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz 3 All electrical values are made by correlation between 2.6v and 5v measurements
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TS4872
ELECTRICAL CHARACTERISTICS VCC = 2.6V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N PSRR Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, f = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Min. Typ. 5.5 10 5 Max. Unit mA nA mV mW % dB
IG S E D
260 0.1 75 70 20 2
Power Supply Rejection Ratio 2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8
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GM GBP
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8 1000 20 Max.
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1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz
VCC = 2.2V, GND = 0V, Tamb = 25C (unless otherwise specified)
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Symbol ICC ISTANDBY Voo Po
Parameter
Supply Current No input signal, no load
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Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8
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THD + N PSRR
Output Power THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Power Supply Rejection Ratio 2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 100mVpp
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Degrees dB MHz
Min.
Typ. 4.5 10 2 180 0.1 75 70 20 2
Unit mA nA mV mW % dB Degrees dB MHz
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GM GBP 4/29
Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the surimposed sinus signal to Vcc @ f = 217Hz
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TS4872
Components Rin Cin Rfeed Cs Cb Cfeed Rstb Gv
Functional Description Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin)) Input coupling capacitor which blocks the DC voltage at the amplifier input terminal Feed back resistor which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed))
Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin)
REMARKS
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1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100F. 2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about 1s.
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5/29
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TS4872
Fig. 1 : Open Loop Frequency Response Fig. 2 : Open Loop Frequency Response
0 60
0 60
-40 -60
Phase (Deg)
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10000
0 10000
0 10000
Gain
40
Gain (dB)
Vcc = 5V RL = 8 Tamb = 25C
-20
Gain
40 Phase
Gain (dB)
Vcc = 5V ZL = 8 + 560pF Tamb = 25C
-20 -40 -60
Phase (Deg)
20
-100 -120
IG S
10 100 1000 Frequency (kHz)
Gain
Phase
-80
-80 -100 -120 -140 -160 -180 -200 -220
20
0
-140 -160
0
-20
-180 -200
-20
-40 0.3
1
10
100
Frequency (kHz)
1000
10000
-220
-40 0.3
1
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Fig. 3 : Open Loop Frequency Response
Fig. 4 : Open Loop Frequency Response
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80 60 40 Gain Vcc = 3.3V RL = 8 Tamb = 25C
0 -20 -40 -60 -80
80 60 40 Phase 20 0
Phase (Deg)
Gain (dB)
Phase 20
-100 -120 -140 -160 -180 -200 -220 -240
0 -20 -40 0.3
F
1
10
100 1000 Frequency (kHz)
10000
Fig. 5 : Open Loop Frequency Response
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80 60 40
Gain (dB)
Gain
Phase 20 0
Phase (Deg)
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-20 -40 0.3
-100 -120 -140 -160 -180 -200 -220 -240
Phase 20 0 -20 -40 0.3
-100 -120 -140 -160 -180 -200 -220 -240
1
10
100 1000 Frequency (kHz)
10000
1
10
100 1000 Frequency (kHz)
6/29
Phase (Deg)
Gain (dB)
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0 -20 -40 -60 -80
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-20 -40 0.3
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1 10
-100 -120 -140 -160 -180 -200 -220 -240
R
100 1000 Frequency (kHz)
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Fig. 6 : Open Loop Frequency Response
80 Gain 60 40 Vcc = 2.6V ZL = 8 + 560pF Tamb = 25C
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Vcc = 2.6V RL = 8 Tamb = 25C
-20 -40 -60 -80
Phase (Deg)
Gain (dB)
Pr
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Vcc = 3.3V ZL = 8 + 560pF Tamb = 25C
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-20 -40 -60 -80
TS4872
Fig. 7 : Open Loop Frequency Response Fig. 8 : Open Loop Frequency Response
100 80 60 Gain
Gain (dB)
-80 Phase -100 -120
Phase (Deg)
100
-80
N
10000
80 60 Gain
Gain (dB)
Phase
-100 -120 -140 -160 -180 -200 -220 -240
Phase (Deg)
40 20 0 -20 -40 0.3
-140 -160 -180 Vcc = 5V CL = 560pF Tamb = 25C 1 10 100 1000 Frequency (kHz) 10000 -200
40 20 0 -20
-40 0.3
1
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10
-220
Vcc = 3.3V CL = 560pF Tamb = 25C
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100 1000 Frequency (kHz)
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100 80 60 Gain
Gain (dB)
-80 Phase -100 -120 -140 -160
40 20 0 -20 -40 0.3 Vcc = 2.6V CL = 560pF Tamb = 25C 1 10
Phase (Deg)
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Fig. 9 : Open Loop Frequency Response
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-180 -200 -220
F
100 1000 Frequency (kHz)
10000
-240
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TS4872
Fig. 10 : Power Supply Rejection Ratio (PSRR) vs Power Supply
-30 Rfeed = 22k Cb = 1F & 0.1F Input = floating RL = 8 Tamb = 25C Vcc=3.3V Ripple=100mVrms -60 Vcc=5V Ripple=200mVrms -70 Vcc=2.6V Ripple=200mVrms -80 10 100 1000 10000 Frequency (Hz) 100000 -70 -80 10
Fig. 11 : Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor
-10 -20 -30
PSRR (dB)
-40
PSRR (dB)
-50
-40 -50 -60
Vcc = 5V Cb = 1F & 0.1F Rfeed = 22k Rfeed = 22k Vripple = 200mVms Input = floating RL = 8 Tamb = 25C
Cfeed=0
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100
Cin=1F Cin=330nF
S
Cfeed=680pF 1000 10000 Frequency (Hz) 100000
D
IG
1000
Cfeed=150pF
Cfeed=330pF
Fig. 12 : Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor
-10 Cb=1F -20 Cb=10F -30
PSRR (dB)
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Fig. 13 : Power Supply Rejection Ratio (PSRR) vs Input Capacitor
-10
R
-40 -50 -60 -70 Cb=100F -80 10
Cb=47F
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100
1000
Frequency (Hz)
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PSRR (dB)
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-10 -20 -30 -40 -50 -60 -70 -80 10
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Fig. 14 : Power Supply Rejection Ratio (PSRR) vs Feedback Resistor
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PSRR (dB)
Vcc = 5 & 2.6V Rfeed = 22k Rin = 22k, Cin = 1F Rg = 100, RL = 8 Tamb = 25C
-20
-30
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Cin=22nF 100
Cin=220nF
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Vcc = 5 & 2.6V Rfeed = 22k, Rin = 22k Cb = 1F Rg = 100, RL = 8 Tamb = 25C
Cin=100nF
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10000 100000
100000
Frequency (Hz)
Vcc = 5V Cb = 1F & 0.1F Vripple = 200mVrms Input = floating RL = 8 Tamb = 25C
Rfeed=110k Rfeed=47k
Rfeed=10k 100 1000 10000 Frequency (Hz) 100000
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TS4872
Fig. 15 : Pout @ THD + N = 1% vs Supply Voltage vs RL
1.4
Output power @ 1% THD + N (W)
Fig. 16 : Pout @ THD + N = 10% vs Supply Voltage vs RL
2.0
1.2 1.0 0.8 0.6 0.4 0.2
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.5
16
IG
3.5
Vcc (V)
Gv = 2 & 10 Cb = 1F F = 1kHz BW < 125kHz Tamb = 25C
1.8 1.6
6 4
6 4
E
3.0 4.0 4.5
S
32 5.0
32 0.0 2.5 3.0 3.5
Vcc (V)
4.0
4.5
5.0
D
Fig. 17 : Power Dissipation vs Pout
1.4 Vcc=5V 1.2 F=1kHz THD+N<1% 1.0 0.8 0.6 0.4 0.2 0.0 0.0
W
Fig. 18 : Power Dissipation vs Pout
0.6 Vcc=3.3V F=1kHz 0.5 THD+N<1%
Power Dissipation (W)
Power Dissipation (W)
RL=4
0.4 0.3 0.2 0.1
RL=8
RL=16 0.8 1.0
0.2
0.4
0.6
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Output Power (W)
Fig. 19 : Power Dissipation vs Pout
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0.0
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Power Dissipation (W)
Flip-Chip Package Power Dissipation (W)
Vcc=2.6V F=1kHz THD+N<1%
Pr e
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1.2
1.4
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1.4 1.2 1.0 0.8 0.6 0.4
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RL=8
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F
R
RL=16 0.4
Output Power (W)
N
8 16
8
Output power @ 10% THD + N (W)
Gv = 2 & 10 Cb = 1F F = 1kHz BW < 125kHz Tamb = 25C
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RL=4
0.6
0.8
Fig. 20 : Power Derating Curves
Heat sink surface = 125mm (See demoboard)
2
RL=4
RL=8
No Heat sink 0.2 0.0
RL=16 0.1 0.2
Output Power (W)
0.3
0.4
0
25
50
75
100
125
150
Ambiant Temperature ( C)
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TS4872
Fig. 21 : THD + N vs Output Power
10 Rl = 4 Vcc = 5V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 22 : THD + N vs Output Power
10 Rl = 4, Vcc = 5V Gv = 10 Cb = Cin = 1F BW < 125kHz, Tamb = 25C
THD + N (%)
THD + N (%)
1
1
20kHz
0.1 20Hz 0.01 1E-3 1kHz
0.1
S
1 0.01 1E-3
20Hz
D
0.01 0.1 Output Power (W)
E
0.01 0.1 Output Power (W)
IG
1kHz 1 Rl = 4, Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
W
Fig. 23 : THD + N vs Output Power
10 Rl = 4, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20kHz
Fig. 24 : THD + N vs Output Power
10
THD + N (%)
THD + N (%)
1
1
0.1
20Hz 0.01 1E-3
1kHz 1
0.01 0.1 Output Power (W)
Fig. 25 : THD + N vs Output Power
O
10
THD + N (%)
THD + N (%)
1
Rl = 4, Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
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0.1 0.01 1E-3
let
Pr e
20kHz 20Hz
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0.1
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20kHz 20Hz 1kHz
F
R
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0.01 0.1 Output Power (W)
N
20kHz
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1
T
Fig. 26 : THD + N vs Output Power
1
Rl = 4, Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
20Hz
0.1
20kHz
1kHz 0.1 0.01 1E-3
1kHz 0.01 Output Power (W) 0.1
0.01 Output Power (W)
10/29
TS4872
Fig. 27 : THD + N vs Output Power
10 Rl = 8 Vcc = 5V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20kHz 0.1
Fig. 28 : THD + N vs Output Power
10 Rl = 8 Vcc = 5V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
THD + N (%)
THD + N (%)
1
1
0.1
S
20Hz 0.01 1E-3 0.01 0.1 Output Power (W) 1kHz 1 0.01 1E-3
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1kHz
20Hz
D
0.01 0.1 Output Power (W)
IG
20kHz 1kHz 1
W
Fig. 29 : THD + N vs Output Power
10 Rl = 8, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 30 : THD + N vs Output Power
10 Rl = 8, Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
THD + N (%)
THD + N (%)
1
1
0.1
20Hz
20kHz
1kHz 0.01 1E-3
0.01 0.1 Output Power (W)
1
Fig. 31 : THD + N vs Output Power
O
10
THD + N (%)
THD + N (%)
1
so Ob
0.1 0.01 1E-3
let
Rl = 8, Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Pr e
20Hz
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0.01 1E-3
0.1
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20Hz
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20kHz
0.01 0.1 Output Power (W)
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1 20Hz 20kHz 1kHz 0.01 Output Power (W) 0.1
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Fig. 32 : THD + N vs Output Power
10 Rl = 8, Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
1
20kHz
0.1
1kHz 0.01 Output Power (W) 0.1 0.01 1E-3
11/29
TS4872
Fig. 33 : THD + N vs Output Power
10 Rl = 8 Vcc = 5V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Fig. 34 : THD + N vs Output Power
10 Rl = 8, Vcc = 5V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C
THD + N (%)
THD + N (%)
1
1
20Hz
0.1
0.1
S
20kHz 0.01 1E-3
D
0.01 0.1 Output Power (W)
1
0.01 1E-3
E
20kHz
1kHz
0.01 0.1 Output Power (W)
IG
20Hz 1kHz 1 Rl = 8, Vcc = 3.3V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C
W
Fig. 35 : THD + N vs Output Power
10 Rl = 8, Vcc = 3.3V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Fig. 36 : THD + N vs Output Power
10
THD + N (%)
THD + N (%)
1
1
0.1
20Hz
20kHz
1kHz 0.01 1E-3
0.01 0.1 Output Power (W)
1
Fig. 37 : THD + N vs Output Power
O
10
THD + N (%)
so Ob
0.1 0.01 1E-3
THD + N (%)
1
let
Rl = 8, Vcc = 2.6V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Pr e
20Hz
N
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so Ob 0.01 1E-3
0.1
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20kHz 1kHz
N
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20Hz
F
R
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0.01 0.1 Output Power (W)
N
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1
T
Fig. 38 : THD + N vs Output Power
10 Rl = 8, Vcc = 2.6V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C 1 20kHz 0.1 1kHz 20Hz
20kHz
1kHz 0.01 Output Power (W) 0.1
0.01 1E-3
0.01 Output Power (W)
0.1
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TS4872
Fig. 39 : THD + N vs Output Power
10 Rl = 16, Vcc = 5V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 40 : THD + N vs Output Power
10 Rl = 16, Vcc = 5V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
1
THD + N (%)
THD + N (%)
1
0.1
20Hz
20kHz
0.1
S
0.01 1E-3 1kHz 0.01 0.1 Output Power (W) 1
0.01 1E-3
E
1kHz
D
0.01 0.1 Output Power (W)
IG
20kHz 20Hz 1
W
Fig. 41 : THD + N vs Output Power
10 Rl = 16, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 42 : THD + N vs Output Power
10 Rl = 16 Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
1
THD + N (%)
THD + N (%)
1
0.1 20Hz
20kHz
0.01 1E-3
1kHz
0.01 Output Power (W)
0.1
Fig. 43 : THD + N vs Output Power
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10
1
THD + N (%)
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0.1 0.01
THD + N (%)
let
1kHz
Rl = 16 Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Pr e
N
od
20kHz
uc
s) t(
so Ob 0.01 10
0.1
O
te le
ro P
N
uc d
20Hz 20kHz
R
E
1kHz 0.01 Output Power (W) 0.1
F
1E-3
T
Fig. 44 : THD + N vs Output Power
1
Rl = 16 Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20Hz
20Hz
0.1 20kHz 1kHz 0.01 1E-3
1E-3
0.01 Output Power (W)
0.1
0.01 Output Power (W)
N
s) t(
0.1
13/29
TS4872
Fig. 45 : THD + N vs Frequency Fig. 46 : THD + N vs Frequency
1
THD + N (%)
THD + N (%)
RL = 4, Vcc = 5V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
1 Pout = 1.2W
0.1 Pout = 600mW
0.1 RL = 4, Vcc = 5V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C 0.01 20
IG
1000 Frequency (Hz) 1000 Frequency (Hz) 1000 Frequency (Hz)
0.01 20
100
D
1000 Frequency (Hz)
10000
E
100 100 100
S
10000
W
Fig. 47 : THD + N vs Frequency
Fig. 48 : THD + N vs Frequency
1
N
THD + N (%)
Pout = 540mW 0.1
THD + N (%)
RL = 4, Vcc = 3.3V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
1
Pout = 540mW
R
0.1
Pout = 270mW 10000
100
F
0.01 20
1000 Frequency (Hz)
Fig. 49 : THD + N vs Frequency
O
1
let so Ob
THD + N (%)
0.1
Pout = 240 & 120mW
THD + N (%)
RL = 4, Vcc = 2.6V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
od Pr e
100
uc
s) t(
Ob -
so
0.01 20
O
te le
ro P
RL = 4, Vcc = 3.3V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C
uc d
E
T
Fig. 50 : THD + N vs Frequency
N
1
RL = 4, Vcc = 2.6V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C
0.1
Pout = 240 & 120mW 0.01 20
0.01 20
1000 Frequency (Hz)
10000
14/29
N
Pout = 600mW
Pout = 1.2W
s) t(
Pout = 270mW
10000
10000
TS4872
Fig. 51 : THD + N vs Frequency
1 RL = 8 Vcc = 5V Gv = 2 Pout = 900mW BW < 125kHz Tamb = 25C
Fig. 52 : THD + N vs Frequency
1 RL = 8 Vcc = 5V Gv = 2 Pout = 450mW BW < 125kHz Tamb = 25C
Cb = 0.1F
THD + N (%)
Cb = 0.1F
THD + N (%)
0.1
0.1
0.01 20
100
D
1000 Frequency (Hz)
10000
0.01 20
E
100
Cb = 1F
Cb = 1F
S
1000 Frequency (Hz) 10000
IG
Cb = 0.1F
W
Fig. 53 : THD + N vs Frequency
Fig. 54 : THD + N vs Frequency
1
Cb = 0.1F
N
THD + N (%)
THD + N (%)
RL = 8, Vcc = 5V Gv = 10 Pout = 900mW BW < 125kHz Tamb = 25C
1
R
0.1
0.1
Cb = 1F 0.01 20 100
1000 Frequency (Hz)
10000
Fig. 55 : THD + N vs Frequency
O
1
let so Ob
THD + N (%)
THD + N (%)
Pr e
N
od
uc
s) t(
so Ob 0.01 20
1
O
te le
Cb = 1F 100
ro P
uc d
RL = 8, Vcc = 5V Gv = 10 Pout = 450mW BW < 125kHz Tamb = 25C
F
E
1000 Frequency (Hz)
T
Fig. 56 : THD + N vs Frequency
Cb = 0.1F
RL = 8, Vcc = 3.3V Gv = 2 Pout = 400mW BW < 125kHz Tamb = 25C
Cb = 0.1F
RL = 8, Vcc = 3.3V Gv = 2 Pout = 200mW BW < 125kHz Tamb = 25C
0.1
0.1
Cb = 1F 0.01 20 100
Cb = 1F 1000 Frequency (Hz) 10000 0.01 20 100 1000 Frequency (Hz) 10000
N
s) t(
10000
15/29
TS4872
Fig. 57 : THD + N vs Frequency Fig. 58 : THD + N vs Frequency
1
Cb = 0.1F
THD + N (%)
THD + N (%)
RL = 8, Vcc = 3.3V Gv = 10 Pout = 400mW BW < 125kHz Tamb = 25C
1
Cb = 0.1F
RL = 8, Vcc = 3.3V Gv = 10 Pout = 200mW BW < 125kHz Tamb = 25C
0.1
0.1
Cb = 1F 0.01 20 0.01 20
Cb = 1F
100
D
1000 Frequency (Hz)
10000
E
100
S
1000 Frequency (Hz) 10000
Cb = 0.1F
IG
te le
Cb = 1F 100 1000 Frequency (Hz) 10000
W
Fig. 59 : THD + N vs Frequency
1 RL = 8, Vcc = 2.6V Gv = 2 Pout = 220mW BW < 125kHz Tamb = 25C
Fig. 60 : THD + N vs Frequency
1
THD + N (%)
THD + N (%)
Cb = 0.1F 0.1
0.1
ro P
R
Cb = 1F 0.01 20 100
O
N
uc d
E
RL = 8, Vcc = 2.6V Gv = 10 Pout = 110mW BW < 125kHz Tamb = 25C
1000 Frequency (Hz)
10000
Fig. 61 : THD + N vs Frequency
O
N
1
let so Ob
THD + N (%)
THD + N (%)
od Pr e
Cb = 0.1F 100
uc
s) t(
so Ob 0.01 20
1
T
F
Fig. 62 : THD + N vs Frequency
RL = 8, Vcc = 2.6V Gv = 10 Pout = 220mW BW < 125kHz Tamb = 25C
Cb = 0.1F
RL = 8, Vcc = 2.6V Gv = 10 Pout = 110mW BW < 125kHz Tamb = 25C
0.1
0.1
Cb = 1F
0.01 20
Cb = 1F 100 1000 Frequency (Hz) 10000
0.01 20
1000 Frequency (Hz)
10000
16/29
N
s) t(
TS4872
Fig. 63 : THD + N vs Frequency
0.1
Fig. 64 : THD + N vs Frequency
Pout = 310mW
THD + N (%)
THD + N (%)
0.01
Pout = 310mW
1E-3 20
100
D
1000 Frequency (Hz)
10000
0.01 20
E
100
100 100
Pout = 620mW
S
1000 Frequency (Hz) 10000
Pout = 620mW
RL = 16, Vcc = 5V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C
IG
uc d s) t(
Pout = 270mW 10000 Pout = 160mW 10000
0.1
W
Fig. 65 : THD + N vs Frequency
0.1
Fig. 66 : THD + N vs Frequency
1 RL = 16, Vcc = 3.3V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
THD + N (%)
E
THD + N (%)
Pout = 135mW 0.01
0.1
Pout = 270mW
O
RL = 16, Vcc = 3.3V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C 10000
F
1E-3 20
100
1000 Frequency (Hz)
Fig. 67 : THD + N vs Frequency
O
0.1
let so Ob
THD + N (%)
0.01
THD + N (%)
Pr e
100
N
od
uc
s) t(
so Ob 0.01 20 1
te le
ro P
R
N
Pout = 135mW
1000 Frequency (Hz)
T
Fig. 68 : THD + N vs Frequency
Pout = 80mW 0.1
RL = 16, Vcc = 2.6V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
Pout = 160mW
RL = 16, Vcc = 2.6V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C 1000 Frequency (Hz) 10000 0.01 20
Pout = 80mW 1000 Frequency (Hz)
1E-3 20
N
17/29
RL = 16, Vcc = 5V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
TS4872
Fig. 69 : Signal to Noise Ratio vs Power Supply with Unweighted Filter (20Hz to 20kHz)
100
Fig. 70 : Signal to Noise Ratio Vs Power Supply with Unweighted Filter (20Hz to 20kHz)
90
90
RL=16
SNR (dB)
RL=8
RL=4
SNR (dB)
80
IG
4.0
Vcc (V)
80
70
RL=16
RL=4
3.0
3.5
Vcc (V)
4.0
4.5
5.0
D
50 2.5
50 2.5
E
3.0 3.5
60
Gv = 2 Cb = Cin = 1F THD+N < 0.4% Tamb = 25C
S
te le
RL=16 3.0
70
60
N
RL=8 Gv = 10 Cb = Cin = 1F THD+N < 0.7% Tamb = 25C 4.5 5.0
Fig. 71 : Signal to Noise Ratio vs Power Supply with Weighted Filter type A
110
E
Fig. 72 : Signal to Noise Ratio vs Power Supply with Weighted Filter Type A
100
100 RL=16
SNR (dB)
90
SNR (dB)
90
R
RL=8
RL=4
ro P
RL=4
N
uc d
s) t(
80
70
Gv = 2 Cb = Cin = 1F THD+N < 0.4% Tamb = 25C 4.0 4.5
T
60 2.5
3.0
3.5
Vcc (V)
Gain (dB)
Icc (mA)
let so Ob
10 5 0 -5 -10 -15 -20 -25 10
N
Fig. 73 : Frequency Response Gain vs Cin, & Cfeed
ro P e
Cin = 470nF Cin = 22nF
uc d
O
s) t(
so Ob 80 70 60 2.5
W
RL=8
O
Gv = 10 Cb = Cin = 1F THD+N < 0.7% Tamb = 25C 3.5
Vcc (V)
F
5.0
4.0
4.5
5.0
Fig. 74 : Current Consumption vs Power Supply Voltage
7 6 Vstandby = 0V Tamb = 25C
Cfeed = 330pF Cfeed = 680pF Cfeed = 2.2nF
5 4 3 2
Cin = 82nF
Rin = Rfeed = 22k Tamb = 25C 10000
1 0
100 1000 Frequency (Hz)
0
1
2
Vcc (V)
3
4
5
18/29
TS4872
Fig. 75 : Current Consumption vs Standby Voltage @ Vcc = 5V
7 6 5
Icc (mA)
Fig. 76 : Current Consumption vs Standby Voltage @ Vcc = 3.3V
6 5 4
Icc (mA)
4 3 2 1 0 0.0
3 2 1 0 0.0
D
E
0.5 1.0 1.5 2.0 2.5 3.0
Vstandby (V)
1.0 0.9 Tamb = 25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.0 3.5 4.0 RL = 16 4.5 5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vstandby (V)
S
te le ro P uc d s) t(
RL = 4 RL = 8
Power supply Voltage (V)
5 4
Icc (mA)
2 1 0 0.0
F
O
3
0.5
1.0 1.5 Vstandby (V)
O
Vout1 & Vout2 Clipping Voltage High side (V)
let so Ob
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5
N
Fig. 79 : Clipping Voltage vs Power Supply Voltage and Load Resistor
od Pr e
RL = 8
ct u
2.0
s) (
2.5
so Ob -
T
Tamb = 25C
RL = 4
RL = 16 3.0 3.5 4.0 4.5 5.0
Power supply Voltage (V)
Vout1 & Vout2 Clipping Voltage Low side (V)
Vcc = 2.6V Tamb = 25C
R
N
6
E
Fig. 77 : Current Consumption vs Standby Voltage @ Vcc = 2.6V
W
Fig. 78 : Clipping Voltage vs Power Supply Voltage and Load Resistor
IG
19/29
N
Vcc = 5V Tamb = 25C
Vcc = 3.3V Tamb = 25C
TS4872
APPLICATION INFORMATION Fig. 80 : Demoboard Schematic
Vcc S1 Vcc C1 R2 C2
S2 GND
Neg. input J1
Vcc
Neg. input J2 R3 C3 R4 C4 Pos input J3 S5 Positive Input mode C5 R5
C6 + 100 6
Vcc
C7 100n
E D
Av=-1 + Vout2 TS4872
S
U1 S6 C9 + 470 OUT1 S3 GND S4 GND S7 4 C10 + 470 Vout1 8
1 7
VinVin+
+
IG
te le ro P uc d s) t(
R1
Pos input J4 Vcc R7 100k S8 Standby + C12 1u
3 5
Bypass
E
Standby
N
C8 100n
+
C11 1u
R
F
O
Fig. 81 : Flip Chip Demoboard Components Side
let so Ob
ro P e
20/29
N
uc d
O
s) t(
so Ob -
Fig. 82 : Flip Chip Demoboard Top Layer
T
GND
W
R6
Bias
2
N
TS4872
Fig. 83 : Flip Chip Demoboard Bottom Layer The differential output voltage is Rfee d Vout2 - Vo ut1 = 2Vin ------------------- (V) Rin The differential gain named gain (Gv) for more convenient usage is : Vout2 - Vou t1 Rfee d G v = -------------------------------------- = 2 ------------------Vin Rin Remark : Vout2 is in phase with Vin and Vout1 is 180 phased with Vin. It means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1.
W
In low frequency region, the effect of Cin starts. Cin with Rin forms a high pass filter with a -3dB cut off frequency 1 FCL = ------------------------------- ( Hz ) 2 R in Cin
D
Low and high frequency response
E
S
IG
E
BTL Configuration Principle
R
The TS4872 is a monolithic power amplifier with a BTL output type. BTL (Bridge Tied Load) means that each end of the load is connected to two single ended output amplifiers. Thus, we have :
F
And Vout1 - Vout2 = 2Vout (V) The output power is :
Pout = ( 2 Vout RMS ) 2 (W ) RL
O
Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V)
O
For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration.
so Ob
Gain In Typical Application Schematic (cf.
page 1) and VOUT IOUT = ---------------- (A) RL and VPEAK 2 POUT = ---------------------- (W) 2 RL
let
od Pr e
ct u
s) (
so Ob -
In high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel on Rfeed. Its form a low pass filter with a -3dB cut off frequency
te le
ro P
N
uc d
1 FCH = ---------------------------------------------- ( Hz ) 2 Rfe ed Cfeed
Power dissipation and efficiency
Hypothesis : * Voltage and current in the load are sinusoidal (Vout and Iout) * Supply voltage is a pure DC source (Vcc) Regarding the load we have : VOUT = V PEAK sin t (V)
In flat region (no effect of Cin), the output voltage of the first stage is : R fe ed Vout1 = - Vin ------------------- (V) Rin For the second stage : Vout2 = -Vout1 (V)
N
T
N
s) t(
21/29
TS4872
Then, the average current delivered by the supply voltage is: ICC
AVG
filtered. Cb has an influence on THD+N in lower frequency, but its function is critical on the final result of PSRR with input grounded in lower frequency. If Cb is lower than 1F, THD+N increase in lower frequency (see THD+N vs frequency curves) and the PSRR worsens up If Cb is higher than 1F, the benefit on THD+N in lower frequency is small but the benefit on PSRR is substantial (see PSRR vs. Cb curve : fig.12) Note that Cin has a non-negligible effect on PSRR in lower frequency. Lower is its value, higher is the PSRR (see fig. 13).
VPEAK = 2 ------------------- (A) RL
and the maximum value is obtained when: Pdiss --------------------- = 0 POUT and its value is:
Pop and Click performance
2RL (W)
D
E
S
2 2 Vcc Pdi ss = ---------------------- POUT - POUT (W) RL
IG
Then, the power dissipated by the amplifier is Pdiss = Psupply - Pout (W)
Pdiss max =
W
2 Vcc
2
F
The maximum theoretical value is reached when Vpeak = Vcc, so
O
POUT VPEAK = ----------------------- = ---------------------Psup ply 4VCC
R
The efficiency is the ratio between the output power and the power supply
N
Remark : This maximum value is only depending on power supply voltage and load values.
E
Pop and Click performance is intimately linked with the size of the input capacitor Cin and the bias voltage bypass capacitor Cb. Size of Cin is due to the lower cut off frequency and PSRR value request and size of Cb is due to THD+N and PSRR request always in lower frequency. Moreover, Cb determines the speed at which the amplifier turns ON. The slower the speed is , the softer turns ON noise.
T
---- = 78.5% 4
let so Ob
Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 100F, you can expect similar THD+N performances like shown in the datasheet. If Cs is lower than 100F, in high frequency increases, THD+N and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than 100F, those disturbances on the power supply rail are more
N
Two capacitors are needed to bypass properly the TS4872. A power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb.
O
Decoupling of the circuit
ro P e
uc d
s) t(
so Ob -
te le
ro P
uc d
The charge time of Cb is directly proportional to the internal generator resistance 50k. Then, the charging time constant for Cb is b = 50kxCb (s) As Cb is directly connected to the non-inverting input (pin 3 & 7) and if we want to minimize, in amplitude and duration, the output spike on Vout1 (pin 8), Cin must be charged faster than Cb. The charge time constant of Cin is in = (Rin+Rfeed)xCin (s) Thus we have the relation in << b (s)
The respect of this relation permits to minimize the pop and click noise. Remark : Minimize Cin and Cb has a benefit on pop and click phenomena but also on cost and size of the application.
22/29
N
s) t(
TS4872
Example : your target for the -3dB cut off frequency is 100 Hz. With Rin=Rfeed=22 k, Cin=72nF (in fact 82nF or 100nF). With Cb=1F, if you choose the one of the latest two values of Cin, the pop and click phenomena at power supply ON or standby function ON/OFF will be very small 50 kx1F >> 44kx100nF (50ms >> 4.4ms). Increase Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. Why Cs is not important in pop and click consideration ? Hypothesis : * Cs = 100F * Supply voltage = 5V * Supply voltage internal resistor = 0.1 * Supply current of the amplifier Icc = 6mA First of all, we must calculate the minimum power supply voltage to obtain 0.5W into 8. With curves in fig. 15, we can read 3.5V. Thus, the power supply voltage value min. will be 3.5V.
with 3.5V we have Pdissmax=0.31W. Referring to power derating curves (fig. 20), with 0.31W the maximum ambient temperature will be 100C. This last value could be higher if you follow the example layout shown on the demoboard (better dissipation). The gain of the amplifier in flat region will be VOUTPP 2 2 RL P OUT G V = -------------------- = ----------------------------------- = 5.65 VINPP VINPP We have Rin > 10k. Let's take Rin = 10k, then Rfeed = 28.25k. We could use for Rfeed = 30k in normalized value and the gain will be Gv = 6. In lower frequency we want 20 Hz (-3dB cut off frequency). Then 1 CIN = ----------------------------- = 795nF 2 RinFCL So, we could use for Cin a 1F capacitor value that gives 16Hz. In Higher frequency we want 20kHz (-3dB cut off frequency). The Gain Bandwidth Product of the TS4872 is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of Rfee d ----------------- = 3 R in and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 660kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed.
23/29
D
E
S
Pdiss max =
IG
2 Vcc 2 2RL
Following equation
the
maximum
power
W
At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (s = 0.1xCs (s)). Then, this time equal 50s to 100s << b in the majority of application.
O
5Cs tDischCs = ------------- = 83 ms Icc
let so Ob
Given : * * * * * *
Now, we must consider the discharge time of Cb. At power OFF or standby ON, Cb is discharged by a 100k resistor. So the discharge time is about bDisch 3xCbx100k (s). In the majority of application, Cb=1F, then bDisch300ms >> tdischCs.
Power amplifier design examples
N
Load impedance : 8 Output power @ 1% THD+N : 0.5W Input impedance : 10k min. Input voltage peak to peak : 1Vpp Bandwidth frequency : 20Hz to 20kHz (0, -3dB) Ambient temperature max = 50C
T
At power OFF of the supply, Cs is discharged by a constant current Icc. The discharge time from 5V to 0V of Cs is
od Pr e
ct u
s) (
so Ob -
F
O
te le
ro P
R
N
uc d
E
N
(W)
dissipation
s) t(
TS4872
Then 1 C FE E D = -------------------------------------- = 265pF 2 R F E E DFC H So, we could use for Cfeed a 220pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula b = 50kxCb >> in = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >> 0.8F. We can choose for Cb a normalized value of 2.2F that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Remark : components with (*) marking are optional. Application n2 : 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier. Components :
Designator R1 R4 R6 R7 C5 C6 C7
E D
te le
Designator
S
IG
470nF 100F 100nF
110k / 0.125W 22k / 0.125W Short Cicuit
330k / 0.125W
W
C9
Short Circuit Short Circuit
C10 C12
Application n1 : 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier.
S1, S2, S6, S7 S8
ro P
1F
N
2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch
uc d
Components :
Designator R1 R4 R6 R7 C5 C6 C7
R
E
Part Type
F
22k / 0.125W 22k / 0.125W Short Cicuit
O
so Ob
C9 C10 C12 S8 J1 U1
let
od Pr e
470nF 100F 100nF 1F
330k / 0.125W
ct u
s) (
so Ob J1 U1 R1 R2 R4 R6 R7 C2 C5
O
SMB Plug TS4872IJ
T
Application n3 : 50Hz to 10kHz bandwidth and 10dB gain BTL power amplifier. Components :
Part Type 33k / 0.125W Short Circuit 22k / 0.125W Short Cicuit 330k / 0.125W 470pF 150nF 100F 100nF Short Circuit
N
Short Circuit Short Circuit
S1, S2, S6, S7
2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB plug TS4872IJ
C6 C7 C9
24/29
N
Part Type
s) t(
TS4872
Designator C10 C12 S1, S2, S6, S7 S8 J1 U1
Part Type Short Circuit 1F 2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch SMB Plug TS4872IJ S8 C6 C7 C9 C10 C12
Designator 100F
Part Type
Short Circuit
S1, S2, S6, S7
E D
te le
Application n4 : Differential inputs BTL power amplifier. In this configuration, we need to place these components : R1, R4, R5, R6, R7, C4, C5, C12. We have also : R4 = R5, R1 = R6, C4 = C5. The gain of the amplifier is :
J1, J3
S
IG
1F SMB Plug TS4872IJ
Short Circuit
2mm insulated Plug 10.16mm pitch 2 pts connector 2.54mm pitch
W
U1
E
Note on how to use the PSRR curves
(page 8)
R
R1 GVDIFF = 2 ------- (Pos. Input - Neg.Input) R4
We have finished a design and we have chosen the components :
ro P
N
uc d
For a 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier you could follow the bill of material below.
Components :
Designator
T
Part Type 22k / 0.125W
O
R1 R4 R5 R6
so Ob
C4 C5
R7
let
ro P e
22k / 0.125W 22k / 0.125W 22k / 0.125W
N
uc d
s) t(
so Ob -
Rin=Rfeed=22k Cin=100nF Cb=1F
Now, on fig. 13, we can see the PSRR (input grounded) vs frequency curves. At 217Hz we have a PSRR value of -36dB. In reality we want a value about -70dB. So, we need a gain of 34dB ! Now, on fig. 12 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=100F, we can reach the -70dB value. The process to obtain the final curve (Cb=100F, Cin=100nF, Rin=Rfeed=22k) is a simple transfer point by point on each frequency of the curve on fig. 13 to the curve on fig. 12. The measurement results is shown on figure 84.
F
O
330k / 0.125W 470nF 470nF
N
s) t(
25/29
100nF
TS4872
Fig. 84 : PSRR changes with Cb Fig. 85 : PSRR measurement schematic
-30 Cin=100nF Cb=1F
-40
PSRR (dB)
Vcc 1 Rin Cin 7 VinVin+ +
IG
Av=-1 +
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Vout1 8 VsRL Vout2 4 Vs+ TS4872
-50 Cin=100nF Cb=100F
-60
3
Bypass
-70 10 100 1000
Frequency (Hz)
E
Rg 100 Ohms
5
Standby
10000
100000
Cb
D
What is the PSRR ? The PSRR is the Power Supply Rejection Ratio. It's a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output.
W
Note on PSRR measurement
GND
2
S
Bias
Vcc
Vcc = 5 & 2.6V Rfeed = 22k, Rin = 22k Rg = 100, RL = 8 Tamb = 25C
Rfeed Vripple 6
Principle of operation
N
* We fixed the DC voltage supply (Vcc) * We fixed the AC sinusoidal ripple voltage (Vripple) * No bypass capacitor Cs is used The PSRR value for each frequency is : PSRR ( d B ) = 20 x Log 10
O
We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR ?
T
For PSRR measurement schematic see figure 85
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26/29
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R ms ( Vrippl e ) -------------------------------------------Rms ( Vs + - Vs - )
Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 125 kHz) Rms measure. It means that we measure the effective Rms signal + the noise.
F
TS4872
TOP VIEW OF THE DAISY CHAIN MECHANICAL DATA ( all drawings dimensions are in millimeters )
7
Vin
+
6
Vcc
5
Vin
GND
BYPASS
1
2
D
3
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ro P uc d s) t(
R
REMARKS Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested.
N
E
W
3.02
ORDER CODE
Part Number TSDC4872IJT
F
Temperature Range -40, +85C
Package J
let so Ob
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*
so Ob Marking DC01
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27/29
8
Vout1
Vout2
4
IG
1.52
STDBY
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TS4872
TAPE & REEL SPECIFICATION ( top view )
User direction of feed
7 6 5
D
8
XXX4872
E
4 3
S
ro P
4
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5 te le 3
1
N
7
E
R
8
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28/29
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1
XXX4872 so Ob 2
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2
6
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TS4872
PIN OUT (top view)
7
Vin
+
MARKING (top view)
6
Vcc
5
8
Vout1
Vout2
4
Vin
GND
BYPASS
1
2
3
PACKAGE MECHANICAL DATA FLIP CHIP - 8 BUMPS
D
E
Balls are underneath
Y : Year W : Week with two digits Example : 1254872
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Die size : (3.02mm10%) x (1.52mm 10%) Die height (including bumps) : 540m 50m Bump height : 140m 15m (i.e. bump diameter of 185m 15m) Silicon thickness : 400m25m Pitch: 500m 10m and 750m10m
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W
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States (c) http://www.st.com
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R
N
N
STDBY

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